CDADIC Project: Low-Noise Multiple-Output Switched-Capacitor Power Management System for SoC

                                          

 

Figure 1. DVFS speed requirement in future SoCs and the proposed SCVR

Figure 2. Voltage scaling speed of the proposed SCVR with tapping network compared with the conventional approaches

 

 

 

 

 

Sponsors

BOEING

NSF

CDADIC

SRC

US ARMY

NIH

JCATI

NRF

LINEAR SIGNAL

SIMIT

KFRI